1. Field of the Invention
The present invention relates to a semiconductor device and particularly relates to a semiconductor device having a plurality of word lines selectively activated.
2. Description of Related Art
In recent years, many electronic apparatuses employ semiconductor device such as a DRAM (Dynamic Random Access Memory) as a memory device. A DRAM stores data by holding electric charges in memory cells arranged at intersection points of a plurality of word lines and a plurality of bit lines. Accordingly, access to a desired memory cell is made by selecting a word line and a bit line based on address information.
Word lines are connected to word drivers. Word drivers drive a selected word line based on address information supplied thereto. Note that techniques related to the memory cell and the word driver are described in Japanese Patent Application Laid-open No. H11-111944, Japanese Patent Application Laid-open No. H11-68063 and Japanese Patent Application Laid-open No. 2008-135099.
In accordance with higher integration of memory cells, the increasing number of word lines leads to place a larger load on word drivers that drive word lines. The increasing number of word lines leads to expand a circuit scale in the semiconductor device. In addition, the size in a direction to repeat word drivers is restricted by the size of memory cells and therefore the size that can be ensured for word drivers is reduced due to higher integration of memory cells. As a result, under a limited repeating pitch and limited wiring layers, it is difficult to pull out word lines from both sides of one word driver. Therefore, such a problem is often dealt with by juxtaposing two word drivers to simply pull out word lines only from one side of each driver. However, if a repeating pitch is further reduced with a larger reduction rate to process memory cells than drivers, the method of putting two word drivers side by side imposes restrictions on further reduction of a circuit scale in the semiconductor device.
Note that in a hierarchical word line structure, word lines are composed of MWL (Main Word Line) and SWL (Sub-Word Line). A plurality of SWLs is related to one of MWLs. Based on address information, MWL is selected and one SWL is selected out of a plurality of SWL related to the selected MWL. Even in a memory with such a hierarchical word line structure, a similar problem arises with MWL and main word drivers.